Current HLS tools fail to synthesise efficient architectures for irregular codes because they rel... Private 3 1 0 Accelerating Irregular Codes on Elastic Dataflow Architectures robert szafarczyk Created: 07/04/2022
A novel algorithm to aggressively reduce on-chip block RAM (BRAM) and off-chip DRAM utilisation o... Private 0 0 0 Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns robert szafarczyk Created: 03/08/2022