A VHDL-described 8-issue VLIW soft-processor for fast packet processing. The processor has been fully synthesized on a NetFPGA-SUME with a clock frequency of 250MHz. Actually, we are seeking different platforms such as Intel FPGA's for developing. Also, we are lokking for Intel smart NICs to test and improve the design.
For an old architectural and performance overview, please refer to the full paper named "Smashing SDN “built-in” actions: programmable data plane packet manipulation in hardware" presented at IEEE Netsoft 2017.
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Cupertino, CA, USA