Open Packet Processor

Open Packet Processor

An hardware implementation of a stateful dataplane based on XFSM.

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Description

Open Packet Processor represents our attempt to synthesize a stateful data plane on FPGA platform. The target platform is NetFPGA SUME. Currently, we are working to improve the usage of TCAM and hash tables. For a full description, please refer to: https://arxiv.org/abs/1605.01977

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