Overview / Usage

We start from the basics, namely matrix vector multiplication. The idea is to find out whether the FPGAs can be effectively used for fitting in the matrices and streaming the vector inputs through it yielding the product as an output. The first step here would be to diagnose the way the compiler handles the matrices. We provide a kernel function to it with hardcoded values of the matrix (factor) and vector values (multiplier) as an argument of the function. One of the goals is to analyse the patterns of the resulting hardware with respect to different matrices used. Among the research questions here the following can be mentioned:

• can the resource usage, technology mapping etc. be predicted with respect to given matrix and board properties?
• in case of partial resource utilization what are the means for scaling the application?
• would it be possible to isolate mapped matrices in a predictable fashion, porting more matrix-vector multiplication operators taking advantage of the unexplotied resourses?