Overview / Usage

Fibonacci sequence generator implemented on the Intel DE10-Lite FPGA Board and its character display module.

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1. The Fibonacci Number generator generates N elements of the Fibonacci series entered by the user using the switches present on the DE10-Lite board (Signal N (4 downto 0)). Signal N is in the range 1-30.

2. The numbers are then displayed one after the other with some delay on the three 7-segment displays (output signal SEVEN_SEG_DISPLAY (41 downto 0)) of the DE10-Lite FPGA board when the display control input switch, DC_IN, is set to high.

3. When the display control input, DC_IN, is set to low, user can traverse the Fibonacci series using a switch and a pushbutton present on the board such that, when the switch(S) is high, one press of push button (signal PB) traverses one step in the Fibonacci series in the ascending order and when the switch(S) is low, one press of push button (signal PB) traverses one step in the Fibonacci series in the descending order.

4. Also, the Fibonacci number generator allows to reset to the first element of the series using the RESET switch.

Methodology / Approach

The fibonacci number generator was implemented as an array_of_cnts where the three array elements keep track of the current fibonacci count being displayed, the previous fibonacci count and the step count of where we are in the sequence when being displayed.

The VHDL standard IEEE Std 1076 is used for implementing this project.

Technologies Used

Intel DE10-Lite FPGA Board, Quartus Prime

Documents and Presentations

Repository

https://github.com/12562/ELEC4430/tree/main/Fibonacci%20Number%20Generator