Overview / Usage

Integrated circuits are becoming increasingly complex, putting pressure on the simulation software to keep up. There are a number of open-source options to run the simulation, such as ngspice, but these generally don't utilize modern heterogeneous hardware to accelerate the computation. Graphics processing units (GPU) and eld programmable gate arrays (FPGA) are both examples of heterogeneous hardware that have been used to accelerate workloads that involve many operations happening in parallel, such as image processing. The aim of the current project is to identify areas of circuit simulation that are suitable for acceleration with heterogeneous hardware and to measure the performance gains compared to a CPU based solution. There is a cost to sending data on the CPU to be processed, so any gains must be balanced against this. An accelerated simulation engine will enable the opportunity for autonomous chip design using the latest machine learning and reinforcement learning algorithms.

This project is in collaboration with Cadence Design Systems.

Methodology / Approach

The project involves investigating how suitable algorithms used in circuit simulation are for execution on heterogeneous hardware, namely GPUs and FPGAs. Initially, the problem of circuit simulation will be outlined, along with a common solution, then understanding the hardware used is essential for effective utilization. The SYCL framework is used for the acceleration of the simulation engine.

Technologies Used

• ComputeCpp
• oneAPI
• Intel/llvm

Repository

https://github.com/FMarno/SYCL-LU-Decomposition

Other links

• PhD opportunity