Overview

The Generic Circuit Level Tool for Evaluation of Nano-Cross Bar Memory using Memristors is a software tool designed to help researchers and engineers in the field of memristor technology. It is a circuit level tool that automates the process of generating the memristor array circuit in a spice environment, making it easier and faster for researchers to design and simulate memristor circuits.

The tool is significant because it helps to ease the researchers' job and enable faster development of memristor-based technology. It is particularly useful in the simulation of memristor cross bar arrays, which plays an important role in collecting data and studying the characteristics of memristors. As the array size increases, the difficulties increase exponentially in designing the cross bar array circuit manually. Therefore, the tool is a valuable asset to help streamline the circuit design process and help researchers free up valuable time to explore new applications for memristor technology.

Objectives

• To analyse and simulate the electrical characteristics of the available electrical memristor models.
• Design the nano-cross bar array using selected materials and by considering the line resistance, and parasitic capacitances of the array.
• To design the nano-cross bar memory array using the selected memristor model and the size of the array in the electrical simulation tool by an autonomous method.
• To automate the entire process so the developed tool can automatically allow the users to select the array size, memristor model and applied input voltage and generates the output simulation results such as write and read operation.
• To analyse the limitations of the line resistance and the parasitic capacitance effect in the nano-cross bar memory and develop a mitigating solution for the same.

What's Memristor Crossbar Array?

A nanoscale device architecture known as a "nano-crossbar" makes use of an assortment of metal wires or rods arranged in a crossbar pattern with cross points where they connect. 

Fig.1 Illustration of memristor crossbar

Fig.1 above shows the schematic diagram of a memristor cross bar array. In a N x N crossbar structure where memristors are placed in between each pair of vertical bit line (BL) and horizontal world line (WL). Each memristor can be programmed to either HRS or LRS with the control of WLs and BLs voltage. Unlike other semiconductor device, memristor crossbar array requires both the WL and BL to be turned on for both Reading and Writing process. To write a specific memristor in the crossbar, the WL voltage will be controlled such that it will provide enough voltage for a certain period to reach the memristor’s switching threshold. To read data stored in the memristor, the WL voltage will be controlled such that it will provide a reading pulse that will not affect and change the state of the memristor. Output voltage will then be measured across the reference resistor connected at the end of BL. If the memristor is in HRS, the output voltage will be significantly lower than the input reading pulse meaning that the state of memristor is 0. In contrary, if the memristor is in LRS the output voltage will be almost the same as the input and the state of memristor will be 1.

Modelling Memristor Cross Bar Array with parasitic effects

1. Line Resistance mathematical modelling: R = ρl/A

Where R is the resistance of connecting, ρ is the resistivity of connecting wire and it is affected by types of material of connecting wire, l is the length of connecting wire and A is the cross-sectional area of connecting wire

2. Coupling capacitance mathematical modelling: C_p = (ε_o ε_r dl)/r

where ε_o is the permittivity of free space, ε_r is the permittivity of the insulator, d is diameter of wire, l is length of each wire and r is distance between two adjacent wires. For a Nth × Nth dimension crossbar network, l=N(d+r). Hence the equation can be rewritten as:

C_p= ε_o ε_r Nd(1+1/∝), ∝ = r/d

3. Boundary stray capacitance mathematical modelling

Library for different memeristor models

The first step of the project is to search for various types of memristor models to establish a library of different memristor models. During this first stage the project aims to simulate each one of these memristor models in the LTspice simulation circuit one by one to analyse the unique characteristics of each memristor model. Memristors are unique as it can retain its previous state due to its special hysteresis characteristic.

The different memristor models simulated in this research is sourced from an educational blogpost called Knowm (https://knowm.org/memristor-models-in-ltspice/). This blogpost provided 5 different LTspice simulation memristor models, which are Joglekar Window, Biolek Window, Yakopic, University of Michigan, and Knowm memristor models.

Following that, each one of these memristor models are to be simulated in LTspice one by one to analyse the unique characteristics of each memristor unit. Memristors are unique because they are capable of retaining their previous state due to their special hysteresis characteristic. Hence, simulations for each of the 5 memristor models are required to confirm that hysteresis is present in each of the memristor simulations when the memristor is operating under ideal conditions.

The first step in simulating the memristor models in LTspice is to generate its corresponding symbol in the LTspice library from its sub file. The memristor symbol generated is shown in the image below. It is in a rectangle shape and have 3 pins in total, the pins are labelled as the Top Electrode (TE), Bottom Electrode (BE) and the XSV pin. The TE and BE is a representation of a real memristor’s top and bottom electrodes, while the XSV pin is used to read the voltage across the memristor which can be used to determine the state of the memristor.

Methodology

Fig. 2 Flow Chart of the methodology of the entire project

The above image is a block diagram of the methodology carried out in this research project. In the first half of this research, modelling of memristors using the LTspice simulation software is carried out to closely examine and study the characteristics of singular memristor unit or multiple memristor in a cross bar setting. In this part, the research will also explore the effect of physical losses present in the cross bar structure by including line resistance and parasitic capacitance loss to the simulation circuits.

Following that, the second half of the research will be using python code to automate the process of constructing and simulating memristor cross bar arrays in LTspice based on simulation parameters given by user. The code for the circuit level tool is designed with modularity, scalability and ease of use in mind. This is because the same code can be used to generate the cross bar array of varying sizes for different memristor models. The python code is used to issue commands to the LTspice simulation software to build the memristor array and set the simulation parameters (input signal, stop time and activation state of the memristor) determined by the user.

When the simulation ends, the code will then display the activation states of each memristor in the entire array in a simple-to-understand matrix form. The results previously obtained in the first half of the project are used to confirm that the result generated by the tool is in line with the understanding of memristor properties. This will be important as it will prove that the simulated circuit constructed by the automated code loop is adhering to the characteristics observed and studied in the first half.

Results & Discussions

The proposed circuit level evaluation tool is proved to be successful as it wonderfully achieves both its objectives. The former being to help analysts by automating the memristor array circuit generation process; and the latter being to help simplify the process of analysing the performance of the complex memristor memory array circuit. Furthermore, the circuit level tool provides users with the option to include the parasitic effects which are present in the cross bar array structure to obtain a simulation result factoring the practical losses. This makes the result from the simulation that much more accurate; this is especially important in memristor circuits as the margins for errors are small. First, this research collected a variety of different memristor model to study and compare the unique switching characteristics of the memristor. The I-V characteristics of each memristor model obtained from the spice simulation are recorded. Then, the memristors are used to construct 3 separate kinds of memristor array circuit for further analysis of memristor operations in a cross bar array configuration. The 3 different kinds of memristor array circuit are: Ideal memristor array circuit, Memristor circuit considering parasitic effect (resistance) and Memristor circuit considering parasitic effect (resistance & capacitance). For each of these 3 simulations, a “2x2” and a “4x4” memristor cross bar array circuit are constructed respectively. The aim is to find out how an increased array size would affect the operation of memristors in the cross bar array circuit.

To account for the parasitic effects, 3 practical loss components were added to each memristor cell segment in the simulation circuit. The line resistance is represented by a resistor of 18.22µΩ; the coupling capacitance is represented by a capacitor of 1.68aF; and the boundary stray capacitance is represented by a capacitor of 2.012aF. These 3 components help to simulate the resistive and capacitive effect of the cross bar array structure of the memristor array circuit.

Following that, python code is used to code the circuit level tool. The circuit level tool plays the role of an intermediary between the user and the spice simulation program. Users have the freedom of determine various simulation parameter through the simple and easy to navigate GUI of the circuit level tool. The tool then issues commands to the spice program to generate the desired memristor array circuit, where the size of the array is determined by the user. After running the simulation, the circuit level tool will display the activation states of each memristor in the array circuit and the voltage across the selected bit line. Users can also analyse each element of the simulation circuit by manually probing the desired point to observe the voltage or current across the two points.

Ultimately, this circuit level tool hopes to help greatly progress the advancement of memristor cross bar array research by making the simple simulation circuit generation tool more readily available to the public. This in hopes that, over time interest towards the field of memristor memory technology research will greatly increase as the barrier to entry is lowered and more tools to help support memristor array simulation become more developed.

Repository

</>https://github.com/LyeGuanYan/Memristor.git

Kindly approach me if you wish to know more details. 

It is recommended that you read the user guide and other support resources available to you to get the most out of the software tool. If you have any questions or issues, don't hesitate to reach out to the support team for assistance.